Semiconductor design and manufacture has many goals, including designing high performance, highly integrated, low cost, miniaturized products. Currently, semiconductor devices are mass produced at 0.18 microns or lower, involving well known levels of integration. However, electronic packaging still concerns higher carrier density, smaller overall volume, etc. for high integration. Indeed, to reduce the overall size and the cost, two or more chips may be packaged together for computers and other devices. This kind of packaging will be mainstream in the future. Multi-chip packaging can be employed to integrate processors and memory chips, or logic chips and memory chips (including DRAMs, flash memories, etc.) in a single package. Thus, the cost and the overall size are reduced.
A technique of putting the same memory chips (e.g. two memory chips) in a single package is disclosed in U.S. Pat. No. 6,366,487 ('487) entitled “PLURALITY OF INTEGRATED CIRCUIT CHIPS”, which is herein incorporated by reference. A dual-chip package technique described in the '487 patent includes similar memory chips (dies or devices) to those in single packages, to increase memory capacity. With the dual-chip package technique, memory chips contained in a single package are configured to share external pins (address, control and data pins). In this configuration, the memory chips in a single package are distinguished as a top (or MSB) memory chip and a bottom (or LSB) memory chip, and may use option pads. For example, an option pad of the bottom memory chip is connected to a ground voltage while an option pad of the top memory chip is connected to a power supply voltage. When an externally input address indicates the bottom memory chip (or when an MSB address bit of the input address is identical to a value of the option pad of the bottom memory chip), it is capable of accessing the bottom memory chip by means of the input address. When an externally input address indicates the top memory chip (or when an MSB address bit of the input address is identical to a value of the option pad of the top memory chip), it is capable of accessing the top memory chip by means of the input address.
If single packages include multiple memories (e.g. RAM and flash memory) with different address systems, an option pad as above may not distinguish between them, for example, a RAM and a flash memory of each memory chip. That is, it is capable of distinguishing the bottom and top memory chips by the option pad, but it is impossible to select either one of the RAM and the flash memory in the selected memory chip.
Accordingly, in the case that each memory chip contained in a single package includes two memories (e.g. RAM and flash memory) whose address systems are different from each other, a technique is required to access memories, especially memories in different chips.